The present invention relates to a verification method for an LSI layout pattern using circuit simulation. More particularly, this invention relates to a verification method for an LSI pattern suitable for circuit simulation by extracting subcircuits having clocked gates from a circuit to be verified.
In designing LSIs, it is important that any defect of the circuit performance should be detected and dealt with before a test chip is fabricated. In view of this, circuit data is extracted from a layout pattern and inputted to a circuit simulator. The amount of circuit data to be extracted becomes enormous as the circuit scale becomes large. If all the extracted circuit data is inputted to the circuit simulator, a very long computer processing time and a large amount of memory capacity is required for circuit simulation.
An example of a circuit simulation method is described in Proc. of IEEE, 23rd Design Automation Conference, 1986 pp. 418 to 424. With this method, the area of a subcircuit along a signal flow path on a layout pattern is designated for a combination of specific input signals, and the designated subcircuit performance is verified. The layout pattern within the designated area only is used for extracting the circuit data.
For verification using circuit data transformed from a layout pattern, it is necessary that a figure corresponding to a circuit element is extracted by means of a pattern operating on data of each layer of masks constituting a layout pattern transistor level circuit data is generated by checking the positions of respective elements, and the transistor level circuit data is transformed into the logic gate level circuit data. A circuit transformation method is known whereby MOS transistors sequentially connected via source or drain terminals between an output net to which the drain terminal of PMOS transistors and the drain terminal of NMOS transistors are connected and a power source net are bundled together as a group, and the function of logic gate of each group is checked. A conventional method of checking the function of a logic gate in a CMOS circuit is discussed in Proc. of IEEE, 19th Design Automation Conference, 1982, pp. 544 to 550. According to this method, it is checked if the connection between PMOS and NMOS transistors is complementary or not. The complementary connection between PMOS and NMOS transistors means the following connections. Namely, PMOS transistors are connected in parallel, and NMOS transistors are connected in series with gate terminals connected to the same net or nets to which the gate terminals of PMOS transistors are connected. Alternatively, PMOS transistors are connected in series, and NMOS transistors are connected in parallel with gate terminals connected to the same net or nets to which the gate terminals of PMOS transistors are connected. A group of n PMOS transistors connected in parallel and n NMOS transistors connected in series constitutes an n-input NAND. A group of n PMOS transistors connected in series and n NMOS transistors connected in parallel constitutes an n-input NOR. A group of one PMOS transistor and one NMOS transistor constitutes an inverter.